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PRELIMINARY
CY7C1199
32K x 8 Static RAM
Features
* High speed -- 15 ns tAA * Single 5V power supply with 3.3V-compatible I/Os -- VOH max. of 3.435V * Fast tDOE three-state drivers. This device has an automatic power-down feature, that reduces the power consumption significantly when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. The CY7C1199 is available in standard 300-mil-wide SOJ packages.
Functional Description
The CY7C1199 is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. The device operates with a single 5V power supply but internally clamps the output voltage level to a maximum of 3.435V. The internal clamps allow the CY7C1199 to interface to 3.3V processors (such as the PentiumTM processor) without buffers or level translators. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and
Logic Block Diagram
Pin Configurations
SOJ Top View
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 C1199-2
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
CE WE OE
I/O1
ROW DECODER
I/O2
SENSE AMPS 1024 x 32 x 8 ARRAY
I/O3 I/O4 I/O5
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A 10
A 11
A 12 A 13
A 14
C1199-1
Selection Guide
Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Pentium is a trademark of Intel Corporation. 7C1199-15 15 130 30 7C1199-20 20 125 30
Com'l Com'l
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 September 27, 1995
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1].................................-0.5V to VCC + 0.5V
CY7C1199
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range[2]
7C1199-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current-- TTL Inputs Automatic CE Power-Down Current-- CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. V CC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. V CC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Com'l Com'l Test Conditions -100 A < IOH < -4.0 mA IOL = 8.0 mA Min. 2.4 2.2 -0.5 -5 -5 Max. 3.435 0.4 VCC +0.3V 0.8 +5 +5 -300 130 30 2.2 -0.5 -5 -5 7C1199-20 Min. 2.4 Max. 3.435 0.4 VCC +0.3V 0.8 +5 +5 -300 125 30 Unit V V V V A A mA mA mA
ISB2
Com'l
10
10
mA
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. See the last page of this specification for Group A subgroup testing information. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters.
2
PRELIMINARY
AC Test Loads and Waveforms[5]
R1317 3.3V OUTPUT 30 pF INCLUDING JIGAND SCOPE Equivalent to: R2 351 3.3V OUTPUT 5 pF INCLUDING JIGAND SCOPE R2 351 3.0V GND 10% R1317
CY7C1199
ALL INPUT PULSES 90% 90% 10% 3ns
C1199-4
3 ns
C1199-3
(a)
(b)
THEVENIN EQUIVALENT 167 1.73V
OUTPUT
Switching Characteristics Over the Operating Range[2, 5]
7C1199-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[8, 9]
7C1199-20 Min. 20 Max. Unit ns 20 3 20 6 0 9 3 9 0 20 20 15 15 0 0 15 9 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 3 ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z
[6]
Min. 15
Max.
15 3 15 5 0 7 3 7 0 15 15 10 10 0 0 9 8 0 7 3
OE HIGH to High Z[6, 7]
[6] [6, 7]
CE HIGH to High Z
CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z
[7] [6]
WE HIGH to Low Z
Notes: 5. Test conditions assume timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL /I OH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, t HZOE is less than tLZOE, and tHZWE is less than t LZWE for any given device. 7. tHZOE, t HZCE, and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t HZWE and t SD.
3
PRELIMINARY
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
CY7C1199
C1199-5
Read Cycle No. 2[11, 12]
CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE V CC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB
C1199-6
tRC
tHZOE tHZCE DATA VALID
HIGH IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)[8, 13, 14]
tWC ADDRESS
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O Note 15 tHZOE DATA IN VALID
C1199-7
tHD
4
PRELIMINARY
Switching Waveforms (continued)
Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in the output state and input signals should not be applied.
CY7C1199
Write Cycle No. 2 (CE Controlled)[8, 13, 14]
tWC ADDRESS CE tSA tAW tHA tSCE
WE tSD DATA I/O DATA IN VALID
C1199-8
tHD
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14]
tWC ADDRESS
CE tAW WE tSA tHA
tSD DATA I/O Note 15 tHZWE DATA INVALID
tHD Note 15 tLZWE
C1199-9
5
PRELIMINARY
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25C ICC NORMALIZED ICC, ISB 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB 25 125 VCC =5.0V VIN =5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC
CY7C1199
OUTPUT SOURCE CURRENT vs.OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
VCC =5.0V 0.8 0.6 -55
25
125
SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO DELTA t AA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
TYPICAL ACCESSTIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC
NORMALIZED I CC vs. CYCLE TIME
25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 VCC =4.5V TA =25C
1.00
VCC =5.0V TA =25C VIN =0.5V
0.75
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
6
PRELIMINARY
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, Output Disabled Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
CY7C1199
Ordering Information
Speed (ns) 15 20 Ordering Code CY7C1199-15VC CY7C1199-20VC Package Name Package Type V21 28-Lead Molded SOJ V21 28-Lead Molded SOJ Operating Range Commercial Commercial
Document #: 38-00460
Package Diagram
28-Lead (300-Mil) Molded SOJ V21
(c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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